1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an apparatus for sensing data of a semiconductor integrated circuit.
2. Related Art
Among semiconductor integrated circuits, DRAM (Dynamic Random Access Memory) devices sense and amplify data, which is stored in memory cells, using sense amplifiers. The sense amplifiers are connected to bit lines of the memory cells respectively, and determine memory cell data by comparing a voltage level at which a charge is shared between the bit lines and a precharge voltage level of a bit line. A sense amplifier block may be connected to one memory block and sense data stored in memory cells within the memory block. The sense amplifier block may also be connected to two memory blocks and selectively sense data stored in memory cells within one of the two memory blocks.
A conventional apparatus for sensing data of a semiconductor integrated circuit includes sense amplifiers. Each of the sense amplifiers includes first and second CMOS inverters that are connected to each other with a latch structure.
There may be a difference between a threshold voltage of the MOS transistor in the first CMOS inverter and a threshold voltage of the MOS transistor in the second CMOS inverter may be. More specifically, as an integration density of the semiconductor integrated circuits increases, channel lengths of the MOS transistors may be slightly changed during a process of manufacturing the MOS transistors. This small change in the channel lengths may cause the difference in threshold voltage between the MOS transistors.
FIG. 1 is a graph illustrating simulation results of threshold voltage offset between right CMOS transistors and between left CMOS transistors (that is, NMOS transistors and PMOS transistors) that constitute a sense amplifier according to the related art. As shown in FIG. 1, the difference in threshold voltage offset between the PMOS transistors is larger than the difference in threshold voltage offset between the NMOS transistors.
The difference in threshold voltage between the PMOS transistors causes a difference in sense amplifier driving signals for driving the sense amplifier. That is, each of the PMOS transistors comprising the sense amplifier has a drain to which an RTO signal is input, and each of the NMOS transistors comprising the sense amplifier has a source to which an SB signal is input. The amount of time required for the RTO signal to become a VDD level is shorter than the amount of time required for the SB signal to become a VSS level, due to the variation of the PMOS transistor. Therefore, even when the NMOS transistors need to be turned on, the PMOS transistors are turned on first, which causes an error in the sense amplifier.
According to another method of the related art, referring to FIGS. 2A and 2B, the technique has been proposed, in which a signal for driving NMOS transistors (for example, SAN) of a CMOS latch is generated, and then, a signal for driving PMOS transistors (for example, SAP) is generated. Therefore, in theory, it is designed so that the NMOS transistors configuring the CMOS latch are turned on earlier than the PMOS transistors.
However, when the semiconductor integrated circuit operates at a high VDD condition, a time difference between the signal for driving the NMOS transistors and the signal for driving the PMOS transistors is reduced. Therefore, in fact, the PMOS transistors are still turned on first, which causes a sensing error.